//******************************************************************************
// Copyright(c) 2013, Hangzhou Guanglu Electronics Co., Ltd.
// All rights reserved
//
// Project Name    :    OLB_10G
// Filename        :    transceiver_top.v
// Designer        :
// Email        :
// Date            :    2013-05-18
// Version        :    1.0
//
// Module Name    :    TRANSCEIVER_TOP
// Description    :    TOP level of ONE TX & ONE RX TO S19250
//
//
// Called by    :    none
//
// Modification History`                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                    
// -----------------------------------------------------------------------------
// 
//

// ***********************************************
// TIMESCALE
// ***********************************************
`timescale    1ns/100ps

// ***********************************************
// INCLUDE
// ***********************************************
`include    "defines.v"

// ***********************************************
// MARCO DEFINITIONs
// ***********************************************


// ***********************************************
// MODULE DEFINITION
// ***********************************************
module FXRECEIVER_TOP_SHELL(
    input           ex_clk200m_p,
    input           ex_clk200m_n,
    output           CLK_FPGA_200M_P,
    output           CLK_FPGA_200M_N,
    
    output          FPGA_TO_S250_CLKP,
    output          FPGA_TO_S250_CLKN,
    
    input   [19:0]  OLB_A,
    inout   [15:0]  OLB_D,
    output          OUT6_CPLD_CLK_FPGA,
    output          OUT5_CPLD_CLK_FPGA,
    input           CLK2OUT124_P,
    input           CLK2OUT124_N,
    input           CK2OUT_TO_FPGA_P,
    input           CK2OUT_TO_FPGA_N,
    input           CLK_FPGA,
    
//    input           OLB_RD_WR,
//    input           OLB_CS,
    output          OLB_INT,

    output          OH_OLB_TO_OAM_FPGA,
    input           OH_OAM_TO_OLB_FPGA,
    input           XC_ACT1_CPLD,
    input           XC_ACT2_CPLD,
    input           SYS_CLK_FP1_OLB_FPGA,
    input           SYS_CLK_FP2_OLB_FPGA,
    output          LINE_OLB_CLK_1_FPGA,
    output          LINE_OLB_CLK_2_FPGA,
    output          LINE_OLB_CLK_FP_1_FPGA,
    output          LINE_OLB_CLK_FP_2_FPGA,
    output          TESTFPGALED1,
    output          TESTFPGALED2,
    output          TESTFPGALED3,
    output          TESTFPGALED4,

    input           TP1,
    input           TP2,
    input           TP3,
    input           TP4,
    input           TP5,
    input           TP6,
    //input           TP7,
    input           TP8,
    input           TP9,
    input           TP10,
    output           TP11,
    output           TP12,
    input           TP13,
    output           TP14,
    input           TP61,
    input           TP60,

    inout           I2C1_SDA_TEMP,
    output          I2C1_SCL_TEMP,
    input           ALT_TEMP,
    inout           INVENTORY_DATA_FPGA,

    inout           SFP_IIC_SDA0_FPGA,
    output          SFP_IIC_SCL0_FPGA,

    input   [16:1]  FPGA_CPLD,
    input   [8:1]   FPGA_TO_CPLD_ADD,

//    input           CLK_FPGA_3P,
//    input           CLK_FPGA_3N,

//    input           CLK_FPGA_4P,
//    input           CLK_FPGA_4N,
    
    
//    input           CLK_FPGA_2P,
//    input           CLK_FPGA_2N,
    input           CLK_FPGA_1P,
    input           CLK_FPGA_1N,

    input           RDWR_B,
    input           CSI_B,

    
    input   [15:0]  S250_TO_FPGA_DATP,
    input   [15:0]  S250_TO_FPGA_DATN,

    input           S250_TO_FPGA_POCLK_P,
    input           S250_TO_FPGA_POCLK_N,

    output  [15:0]  FPGA_TO_S250_DATP,
    output  [15:0]  FPGA_TO_S250_DATN,

    output          FPGA_TO_S250_PICLK_P,
    output          FPGA_TO_S250_PICLK_N,
	
    input           FPGA_TO_S250_PCLK_P,
    input           FPGA_TO_S250_PCLK_N

///    output  [3:0]   DATA_OLB_TO_XC2P,
///    output  [3:0]   DATA_OLB_TO_XC2N,
///    input   [3:0]   DATA_XC2_TO_OLBP,
///    input   [3:0]   DATA_XC2_TO_OLBN,
/// 
///    input           MGTREFCLK0_112P,
///    input           MGTREFCLK0_112N,
///
///    output  [3:0]   DATA_OLB_TO_XC1P,
///    output  [3:0]   DATA_OLB_TO_XC1N,
///    input   [3:0]   DATA_XC1_TO_OLBP,
///    input   [3:0]   DATA_XC1_TO_OLBN,
/// 
///    input           MGTREFCLK0_113P,
///    input           MGTREFCLK0_113N

/*    input                              TRSV_IN_RFCLK_P,
    input                              TRSV_IN_RFCLK_N,

    input                              TRSV_AFE_0_RXDATA_P,
    input                              TRSV_AFE_0_RXDATA_N,
    output                             TRSV_AFE_0_TXDATA_P,
    output                             TRSV_AFE_0_TXDATA_N,

    input                              TRSV_AFE_1_RXDATA_P,
    input                              TRSV_AFE_1_RXDATA_N,
    output                             TRSV_AFE_1_TXDATA_P,
    output                             TRSV_AFE_1_TXDATA_N,

    input                              TRSV_AFE_2_RXDATA_P,
    input                              TRSV_AFE_2_RXDATA_N,
    output                             TRSV_AFE_2_TXDATA_P,
    output                             TRSV_AFE_2_TXDATA_N,

    input                              TRSV_AFE_3_RXDATA_P,
    input                              TRSV_AFE_3_RXDATA_N,
    output                             TRSV_AFE_3_TXDATA_P,
    output                             TRSV_AFE_3_TXDATA_N*/
 );

// ***********************************************
// INTERNAL SIGNAL
// ***********************************************
    


wire    [15:0]      CHNN0_DATA_TX_P;
wire    [15:0]      CHNN0_DATA_TX_N;
wire                CHNN0_CLOCK_TX_P;
wire                CHNN0_CLOCK_TX_N;
//wire    [15:0]      CHNN1_DATA_TX_P;
//wire    [15:0]      CHNN1_DATA_TX_N;
//wire                CHNN1_CLOCK_TX_P;
//wire                CHNN1_CLOCK_TX_N;
//wire    [15:0]      CHNN2_DATA_TX_P;
//wire    [15:0]      CHNN2_DATA_TX_N;
//wire                CHNN2_CLOCK_TX_P;
//wire                CHNN2_CLOCK_TX_N;
//wire    [15:0]      CHNN3_DATA_TX_P;
//wire    [15:0]      CHNN3_DATA_TX_N;
//wire                CHNN3_CLOCK_TX_P;
//wire                CHNN3_CLOCK_TX_N;
   
//wire                d_buff_ready;    
//wire                d_dvt;
//wire                d_sop_outt;
//wire                d_eop_outt;
//wire                d_errt;
//wire    [3:0]       d_modt;
//wire    [127:0]     d_doutt;
//wire                ddvout;

wire                osc_200m;
wire                sdh_622clk;

wire                sfi_refclk_out_0_p;
wire                sfi_refclk_out_0_n;
//wire                sfi_refclk_out_1_p;
//wire                sfi_refclk_out_1_n;
//wire                sfi_refclk_out_2_p;
//wire                sfi_refclk_out_2_n;
//wire                sfi_refclk_out_3_p;
//wire                sfi_refclk_out_3_n;   
wire	[15:0]		mpi_par_keep;
wire    [3:0]       led;
// ***********************************************
// PARAMETER
// ***********************************************


///   assign  FPGA_TO_S250_DATP[15:0]   = S250_TO_FPGA_DATP;

// ***********************************************
// INTERNAL SIGNAL
// ***********************************************
//CLOCK DEFINITION
wire    clk155m_sys;
wire    clk125m_sys;
wire    clk125m;

wire    [7:0]   RXN_IN;
wire    [7:0]   RXP_IN;
wire    [7:0]   TXN_OUT;
wire    [7:0]   TXP_OUT;
reg		clk_test;
reg		clk_test_t;

wire            a_sfi4_rclkg;
wire            a_sfi4_tclk;
wire	[15:0]  DATA_RX_BUF;
reg				clk_test1;
reg				clk_77m_test;
//************************************************** 
//
//**************************************************                          

// IBUFDS #(.DIFF_TERM("TRUE"), .IOSTANDARD("LVDS_25")) RX_CLK_IN(.O(CLOCK_RX_BUF), .I(S250_TO_FPGA_POCLK_P), .IB(S250_TO_FPGA_POCLK_N));
//always @(posedge CLOCK_RX_BUF or posedge reset_h) 
//begin 
//	 if (reset_h == 1'b1)
//    begin
//		  clk_test1 <= 1'b0;
//    end
//    else
//    begin
//		  clk_test1 <= ~clk_test1;
//    end
//end

//assign TESTFPGALED1 = clk_test1;
assign TESTFPGALED1 = ~c200m_lda;
assign TESTFPGALED2 = ~c200m_ldb;
assign TESTFPGALED3 = clk50m;
assign TESTFPGALED4 = clk50m;
 

assign	LINE_OLB_CLK_FP_1_FPGA = SYS_CLK_FP1_OLB_FPGA;
assign	LINE_OLB_CLK_FP_2_FPGA = SYS_CLK_FP2_OLB_FPGA;

assign	OUT6_CPLD_CLK_FPGA = LINE_OLB_CLK_1_FPGA;
assign	OUT5_CPLD_CLK_FPGA = LINE_OLB_CLK_1_FPGA;

assign	OH_OLB_TO_OAM_FPGA = OH_OAM_TO_OLB_FPGA;
    
assign	I2C1_SCL_TEMP = I2C1_SDA_TEMP;

assign	SFP_IIC_SCL0_FPGA = SFP_IIC_SDA0_FPGA;


    assign          LINE_OLB_CLK_1_FPGA = SYS_CLK_FP1_OLB_FPGA;
    assign          LINE_OLB_CLK_2_FPGA = SYS_CLK_FP2_OLB_FPGA;
	
assign TP12 = 	clk_test;
assign TP11 = clk_test_t;
always @(posedge a_sfi4_rclkg or posedge reset_h) 
begin 
	 if (reset_h == 1'b1)
    begin
		  clk_test <= 1'b0;
    end
    else
    begin
		  clk_test <= ~clk_test;
    end
end
	
always @(posedge a_sfi4_tclk or posedge reset_h) 
begin 
	 if (reset_h == 1'b1)
    begin
		  clk_test_t <= 1'b0;
    end
    else
    begin
		  clk_test_t <= ~clk_test_t;
    end
end

(* keep = "TRUE" *)wire                          BKP_TXFP8K;
(* keep = "TRUE" *)wire[15:0]                    BKP_TXDATA_0;
(* keep = "TRUE" *)wire[15:0]                    BKP_TXDATA_1;
(* keep = "TRUE" *)wire[15:0]                    BKP_TXDATA_2;
(* keep = "TRUE" *)wire[15:0]                    BKP_TXDATA_3;
	
	

///clk_155_to_19	U_clk_155_to_19 (
///	// Clock in ports
///  .RESET			(reset_h),
///  .CLK_IN1			(a_sfi4_rclkg),
///  // Clock out ports
///  .CLK_OUT1			(LINE_OLB_CLK_1_FPGA),
///  .CLK_OUT2			(LINE_OLB_CLK_2_FPGA),
///  // Status and control signals
///  
///  .LOCKED			()
/// );


IBUFGDS Ut_CLK155M_IN(
    .O(clk155m_test), 
    .I(CK2OUT_TO_FPGA_P), 
    .IB(CK2OUT_TO_FPGA_N)

    );

    
///IBUFGDS U4_CLK155M_IN(
///    .O(clk155m_4), 
///    .I(CLK_FPGA_4P), 
///    .IB(CLK_FPGA_4N)
///
///    );

IBUFGDS U_CLK155M_124(
    .O(clk155m_124), 
    .I(CLK2OUT124_P), 
    .IB(CLK2OUT124_N)

    );

OBUFDS  U_OBUFDS_155M_CLOCK
	(
	.O(FPGA_TO_S250_CLKP), 
	.OB(FPGA_TO_S250_CLKN), 
	.I(clk155m_124)
	);
    
    
    
clk_25M_TO_200M     U_clk_25M_TO_200M (
// Clock in ports
  .RESET        (reset_h),
  .CLK_IN1      (CLK_FPGA),
  // Clock out ports
  .CLK_OUT1     (CLK_200M),
  .LOCKED       (c200m_lda)
 );

OBUFDS  U_OBUFDS_200M_CLOCK
	(
	.O(CLK_FPGA_200M_P), 
	.OB(CLK_FPGA_200M_N), 
	.I(CLK_200M)
	);
     

IDELAYCTRL RX_IDELAYCTRL(.RDY(), .REFCLK(delay_200m), .RST(reset_h));   //  

clkin200_200_125    U_clkin200_200_125 (
    .RESET          (reset_h),
  
  // Clock in ports
  .CLK_IN1_P        (ex_clk200m_p),
  .CLK_IN1_N        (ex_clk200m_n),
  // Clock out ports
    .CLK_OUT1       (delay_200m),
    .CLK_OUT2       (clk125m),
    .CLK_OUT3       (clk50m),
  // Status and control signals
    .LOCKED         (c200m_ldb)
 );
	

IBUFGDS #(
    .DIFF_TERM("TRUE"),
    .IOSTANDARD("LVDS_25")
//    .IOSTANDARD("LVPECL_25")      
     ) 
    U_CLK155M_IN(
    .O(clk155m_sys), 
    .I(CLK_FPGA_1P), 
    .IB(CLK_FPGA_1N)

    );
///IBUFGDS U3_CLK155M_IN(
///    .O(clk155m_sys), 
///    .I(CLK_FPGA_3P), 
///    .IB(CLK_FPGA_3N)
///
///    );

assign TP14 = clk_77m_test;

always @( posedge reset_h or posedge CLK_200M ) begin
    if ( reset_h==1'b1 )
		clk_77m_test            <= 1'b0;
    else begin
		clk_77m_test <= ~clk_77m_test;
    end
end

	
///assign rst_fpga_n = ~rst_fpga;
///assign FPGA_CPLD1  = 1'b0;
///assign FPGA_CPLD2  = 1'b0; 
///assign FPGA_CPLD3  = 1'b0; 
///assign FPGA_CPLD4  = 1'b0; 
///assign FPGA_CPLD5  = 1'b0; 
///assign FPGA_CPLD6  = CPLD_TO_S250_SDO; 
///assign FPGA_CPLD7  = CPLD_TO_S250_CS; 
///assign FPGA_CPLD8  = CPLD_TO_S250_SCK; 
///assign FPGA_CPLD9  = CPLD_TO_S250_SDI; 
///assign FPGA_CPLD10 = s19250_data_cnt[6]; 
///assign FPGA_CPLD11 = s19250_data_cnt[5]; 
///assign FPGA_CPLD12 = 1'b0; 
///assign FPGA_CPLD13 = OLB_RD_WR; 
///assign FPGA_CPLD14 = CLK_CPLD; 
///assign FPGA_CPLD15 = rst_fpga_n; 
///assign FPGA_CPLD16 = fpga_cs_n;
	
	
assign  reset_h = ~ex_reset_n;
assign  ex_reset_n = FPGA_CPLD[15];
assign	OLB_CS = ~FPGA_CPLD[16];
assign	OLB_RD_WR = FPGA_CPLD[13];
//########################################################################


OLB_REG U_OLB_REG(
// input
    .clk_cpld               (clk155m_sys),
    .reset_h                (reset_h),
    
    .cpld_cs                (OLB_CS),
    .w_r                    (OLB_RD_WR),
	.cpld_addr				(OLB_A[19:0]),
    
    .adio                   (OLB_D[15:0]),
    
    .int                    (OLB_INT),
    
    .fpga_data_empty_flg        (1'b0),

    .fpga_nstatus           (1'b0),
    .fpga_conf_done         (1'b0),

    .fpga_int               (1'b0),
    .cpld_int               (1'b0),
    .glb_int                (1'b0),


	.oe_test				(oe_test),
    .c3b_si_to_cpld         (1'b0),
    .c2b_si_to_cpld         (1'b0),
    .c1b_si_to_cpld         (1'b0),
    .c1a_si_to_cpld         (1'b0),
    .c2a_si_to_cpld         (1'b0),
    .lol_si_to_cpld         (1'b0),
    .int_alm_si_to_cpld     (1'b0),

    .mpi_par_keep           (mpi_par_keep[15:0]),
    .cs0_si_to_cpld         (1'b0),
    .cs1_si_to_cpld         (1'b0),
    
    
    .soft_rst               (),
	.rst_fpga				(),           // rst_fpga_logic
	.rst_cfg				(),
    .rst_si5369             (),
    .cksel_reg              (),
    .cs0_c3a                (),
    .cs1_c4a                (),
    
    .fpga_cfg_mode          (),
    .fpga_init              (),
    .flg_a_set              (),

    .fpga_data_a            (),
    .fpga_data_b            (),
    .fpga_data_c            (),
    .fpga_data_d            (),

    .flg_si_set             (),
    .si5369_data_empty_flg  (1'b0),
    .si5369_data_a          (),
    .si5369_data_r          (16'h0000),
    
    .switch_sel3_cpld       (),
    .switch_sel2_cpld       (),
    .switch_sel1_cpld       (),
    .switch_sel0_cpld       (),
    .s155_622               (),
    .run                    (),
    .run1                   (),
    .active_1               (),
    .active_2               (),
    .active_3               (),
    .active_4               (),
    .alm                    (),
    .alm_1                  (),
    .alm_2                  (),
    .alm_3                  (),
    .alm_4                  (),
    
	 .test1						(),
	 .test2						()
);






//########################################################################

 
FXRECEIVER_TOP  U_FXRECEIVER_TOP(
    
    .ex_reset_n                         (ex_reset_n),
    .osc_200m                           (delay_200m),
	.clk125m							(clk125m),
    .ex_clk155m_p                       (),                          //155MHz P
    .ex_clk155m_n                       (),                          //155MHz N

    .ex_clk622m_p                       (),                          //622MHz P
    .ex_clk622m_n                       (),                          //622MHz N    

    .clk155m_sys                        ( clk155m_sys ),
    
    // interface to SFI interface
    
    .CHNN0_DATA_TX_P                    (FPGA_TO_S250_DATP ),
    .CHNN0_DATA_TX_N                    (FPGA_TO_S250_DATN ),
    .CHNN0_CLOCK_TX_P                   (FPGA_TO_S250_PICLK_P),
    .CHNN0_CLOCK_TX_N                   (FPGA_TO_S250_PICLK_N),
    .CHNN0_DATA_RX_P                    (S250_TO_FPGA_DATP ),
    .CHNN0_DATA_RX_N                    (S250_TO_FPGA_DATN ),
    .CHNN0_CLOCK_RX_P                   (S250_TO_FPGA_POCLK_P),
    .CHNN0_CLOCK_RX_N                   (S250_TO_FPGA_POCLK_N),

    .sfi_refclk_0_p                     (  ),
    .sfi_refclk_0_n                     (),

	.chnn0_tx_pclk_p					(FPGA_TO_S250_PCLK_P),
	.chnn0_tx_pclk_n					(FPGA_TO_S250_PCLK_N),

	
    .sfi_refclk_out_0_p                 (),
    .sfi_refclk_out_0_n                 (),

    .a_sfi4_rclkg						(a_sfi4_rclkg),
	
    .test_sig							(2'b00),
    .led                                (led ),                       // fpga state ind
    
    .a_glb_sfi4_r2tloop                 (1'b0),                     // DDV SFI4 DEBUG TEST
    .a_glb_sfi4_t2rloop                 (1'b0),
    .a_glb_hdlc_r2tloop                 (1'b0),
    .a_glb_hdlc_t2rloop                 (1'b0),
	.mpi_tx_soh_loop_en					(1'b0),

	.los_sd								(),
	.a_sfi4_tclk						(a_sfi4_tclk),
//	.mpi_par_keep						(mpi_par_keep[15:0]			)
	.mpi_par_keep						(16'hffff			),

    .BKP_OUT_TXFP8K                     ( BKP_TXFP8K ),
    .BKP_OUT_TXDATA_0                   ( BKP_TXDATA_0[15:0] ),
    .BKP_OUT_TXDATA_1                   ( BKP_TXDATA_1[15:0] ),
    .BKP_OUT_TXDATA_2                   ( BKP_TXDATA_2[15:0] ),
    .BKP_OUT_TXDATA_3                   ( BKP_TXDATA_3[15:0] )
    );
 

/*

BKP_TOP                                      INST_BKP_TOP(
   .GTM_RESET                                ( !ex_reset_n ),
   .GTM_CLK38M88                             ( CLK_FPGA ),
   .GTM_CLK155M52                            ( clk155m_sys ),
   .GTM_BP_FP8K                              (  ),

   .GMPI_WA                                  (  ),
   .GMPI_WD                                  (  ),
   .GMPI_BP_WE                               (  ),
   .GMPI_RA                                  (  ),
   .GMPI_BP_RD                               (  ),


   .TRSV_IN_RFCLK_P                          ( TRSV_IN_RFCLK_P ),
   .TRSV_IN_RFCLK_N                          ( TRSV_IN_RFCLK_N ),

   .TRSV_AFE_0_RXDATA_P                      ( TRSV_AFE_0_RXDATA_P ),
   .TRSV_AFE_0_RXDATA_N                      ( TRSV_AFE_0_RXDATA_N ),
   .TRSV_AFE_0_TXDATA_P                      ( TRSV_AFE_0_TXDATA_P ),
   .TRSV_AFE_0_TXDATA_N                      ( TRSV_AFE_0_TXDATA_N ),

   .TRSV_AFE_1_RXDATA_P                      ( TRSV_AFE_1_RXDATA_P ),
   .TRSV_AFE_1_RXDATA_N                      ( TRSV_AFE_1_RXDATA_N ),
   .TRSV_AFE_1_TXDATA_P                      ( TRSV_AFE_1_TXDATA_P ),
   .TRSV_AFE_1_TXDATA_N                      ( TRSV_AFE_1_TXDATA_N ),

   .TRSV_AFE_2_RXDATA_P                      ( TRSV_AFE_2_RXDATA_P ),
   .TRSV_AFE_2_RXDATA_N                      ( TRSV_AFE_2_RXDATA_N ),
   .TRSV_AFE_2_TXDATA_P                      ( TRSV_AFE_2_TXDATA_P ),
   .TRSV_AFE_2_TXDATA_N                      ( TRSV_AFE_2_TXDATA_N ),

   .TRSV_AFE_3_RXDATA_P                      ( TRSV_AFE_3_RXDATA_P ),
   .TRSV_AFE_3_RXDATA_N                      ( TRSV_AFE_3_RXDATA_N ),
   .TRSV_AFE_3_TXDATA_P                      ( TRSV_AFE_3_TXDATA_P ),
   .TRSV_AFE_3_TXDATA_N                      ( TRSV_AFE_3_TXDATA_N ),

   .TRSV_AFE_4_RXDATA_P                      (  ),
   .TRSV_AFE_4_RXDATA_N                      (  ),
   .TRSV_AFE_4_TXDATA_P                      (  ),
   .TRSV_AFE_4_TXDATA_N                      (  ),

   .TRSV_AFE_5_RXDATA_P                      (  ),
   .TRSV_AFE_5_RXDATA_N                      (  ),
   .TRSV_AFE_5_TXDATA_P                      (  ),
   .TRSV_AFE_5_TXDATA_N                      (  ),

   .TRSV_AFE_6_RXDATA_P                      (  ),
   .TRSV_AFE_6_RXDATA_N                      (  ),
   .TRSV_AFE_6_TXDATA_P                      (  ),
   .TRSV_AFE_6_TXDATA_N                      (  ),

   .TRSV_AFE_7_RXDATA_P                      (  ),
   .TRSV_AFE_7_RXDATA_N                      (  ),
   .TRSV_AFE_7_TXDATA_P                      (  ),
   .TRSV_AFE_7_TXDATA_N                      (  ),

   .BKP_IN_TXFP8K                            ( BKP_TXFP8K ),
   .BKP_IN_TXDATA_0                          ( BKP_TXDATA_0[15:0] ),
   .BKP_IN_TXDATA_1                          ( BKP_TXDATA_1[15:0] ),
   .BKP_IN_TXDATA_2                          ( BKP_TXDATA_2[15:0] ),
   .BKP_IN_TXDATA_3                          ( BKP_TXDATA_3[15:0] )
   );

*/

 
///assign RXN_IN[7:0] = {DATA_XC2_TO_OLBN[3],DATA_XC2_TO_OLBN[2],DATA_XC2_TO_OLBN[1],DATA_XC2_TO_OLBN[0],DATA_XC1_TO_OLBN[3],DATA_XC1_TO_OLBN[2],DATA_XC1_TO_OLBN[1],DATA_XC1_TO_OLBN[0]};
///assign RXP_IN[7:0] = {DATA_XC2_TO_OLBP[3],DATA_XC2_TO_OLBP[2],DATA_XC2_TO_OLBP[1],DATA_XC2_TO_OLBP[0],DATA_XC1_TO_OLBP[3],DATA_XC1_TO_OLBP[2],DATA_XC1_TO_OLBP[1],DATA_XC1_TO_OLBP[0]};
///
///assign DATA_OLB_TO_XC2P[3] = TXP_OUT[7];
///assign DATA_OLB_TO_XC2P[2] = TXP_OUT[6];
///assign DATA_OLB_TO_XC2P[1] = TXP_OUT[5];
///assign DATA_OLB_TO_XC2P[0] = TXP_OUT[4];
///assign DATA_OLB_TO_XC1P[3] = TXP_OUT[3];
///assign DATA_OLB_TO_XC1P[2] = TXP_OUT[2];
///assign DATA_OLB_TO_XC1P[1] = TXP_OUT[1];
///assign DATA_OLB_TO_XC1P[0] = TXP_OUT[0];
///
///assign DATA_OLB_TO_XC2N[3] = TXN_OUT[7];
///assign DATA_OLB_TO_XC2N[2] = TXN_OUT[6];
///assign DATA_OLB_TO_XC2N[1] = TXN_OUT[5];
///assign DATA_OLB_TO_XC2N[0] = TXN_OUT[4];
///assign DATA_OLB_TO_XC1N[3] = TXN_OUT[3];
///assign DATA_OLB_TO_XC1N[2] = TXN_OUT[2];
///assign DATA_OLB_TO_XC1N[1] = TXN_OUT[1];
///assign DATA_OLB_TO_XC1N[0] = TXN_OUT[0];
///
///
///gtwizard_v2_4_exdes U_gtwizard_v2_4_exdes
///(
///    .Q0_CLK1_GTREFCLK_PAD_N_IN      (MGTREFCLK0_112N),
///    .Q0_CLK1_GTREFCLK_PAD_P_IN      (MGTREFCLK0_112P),
///    .Q1_CLK1_GTREFCLK_PAD_N_IN      (MGTREFCLK0_113N),
///    .Q1_CLK1_GTREFCLK_PAD_P_IN      (MGTREFCLK0_113P),
///    .DRP_CLK_IN                     (clk50m),
///    .SYSCLK_IN                      (clk155m_sys),
///    .TRACK_DATA_OUT                 (track_data_out),
///    .RXN_IN                         (RXN_IN[7:0]),
///    .RXP_IN                         (RXP_IN[7:0]),
///    .TXN_OUT                        (TXN_OUT[7:0]),
///    .TXP_OUT                        (TXP_OUT[7:0])
///);
/// 
// ***********************************************************************
// ENDMODULE
// ***********************************************************************

endmodule 